Questions about zero-power voltage measurement
While looking around for a solution to measure a high-ish voltage battery (56V max, e.g. 4x 12 SLA batteries) without the constant battery-drain I came across this interesting schematic/article and are trying to understand how it works:
DIO is driven high using the internal pull-up resistor, the gate voltage of the mosfet is at Vbatt so Vgs = 0V.
When DIO switches to output mode it will sink some of the energy stored in the capacitor on the DIO side (E=1/2 C(Vbatt-Vss)^2), the voltage on the gate drops and the capacitor starts sucking up current through R. Maximum Vgs is a result of the speed in which the capacitor is drained.
The capacitor is starting to get charged and Vgs reduces. While the voltage Vgs is more then Vth the mosfet is driven in switched mode (fully open), at the end of the recovery phase the mosfet enters amplifier mode (partially open) until it’s fully closed
Return to idle state:
DIO is driven high, reducing the voltage over the capacitor by Vss.
I hope some of the more electronics savvy forum members are willing to answer the following questions:
- Most mosfet’s Vgs-max is usually 20V to 40V and I’m not sure how high Vgs becomes when DIO pulls the gate low and Vbatt is more then 40V?
- Should I add a resistor (e.g. 2 k) between the capacitor and DIO plus a zener to ground for protection of the uC in case the capacitor breaks down? This will probably affect maximum Vgs…
- Would this mosfet work well in this situation: http://www.farnell.com/datasheets/1643264.pdf (€0.75 each)?
- Is the switching behavior as a result from noise on the power supply a problem (discussed in the next blog post)? If so, is there a way to reduce this switching?
- According to the comment from Max (in the previous blog post), driving DIO high (he says tri-state but I’m not sure if that’s correct?) recovers some energy used to charge the capacitor through DIO’s protection diodes. I don’t understand why.
- Is using the protection diodes this way ‘best practice’? I.e. this doesn’t reduce the uC’s lifetime?
Thanks in advance.
Getting that circuit to operate with a Vbatt of 40v is a stretch. The difficulty is that the maximum drive available at the PFET gate is the Vss of the MCU, say 3.3V For a reasonable turn on, this requires a sensitive FET (usually referred to as ‘Logic Level’) and these come with quite low Vds ratings. The Vgs rating is not a problem since Vg is always between Vs and (Vs - Vss).
The FET you reference is conducting nicely at –3.5v drive, and the plots show adequate conduction down at
2.0v Vgs. The sampling window will be relatively narrow since the coupling capacitor is recharged from a high potential, so the useful drive window is reduced in time. you can always add additional protection by using a reverse biased schottky diode between the DIO pin and Vss. The fault current is limited by the gate/source resistor.
If you de-rate the coupling capacitor (e.g. use 150V rating), the chance of failure is low
You will need to calibrate the circuit to allow for variation in the sampling resistor values and your choice of Vref. Ideally, you need an external Vref and some temperature compensation but I would expect reasonable performance without extra circuitry.
Thanks for the feedback. Also thanks for confirming Vgs-max = Vs - Vss. That means the 40Vgs mosfet I selected is not suitable since Vs-max =56V and Vss = 3.3V. I also hadn’t realized how short the sample period would become at those voltages. Accuracy of the measurement isn’t most important in my case.
It seems this leaves three standard options:
1) Use a more standard n-channel mosfet (e.g. BSS138) to drive the p-channel high side switch and add a ~10V zener parallel to R to keep Vgs within specs.
2) Use a more standard n-channel mosfet (e.g. BSS138) to drive a high side switch ic.
2) Use a logic level high side switch ic.
A bit more expensive but also allows control over the sample time window.